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| TECHNICAL DATA KK74LVU04 Hex Inverter N SUFFIX PLASTIC 14 1 14 1 D SUFFIX SOIC The 74LVU04 is a low-voltage, Si-gate CMOS device and is pin compatible with the 74HCU04. The 74LVU04 is a general purpose hex inverter. Each of the six inverters is a single stage with unbuffered outputs. * * * * Wide Operating Voltage: 1.0/5.5 V Optimized for Low Voltage applications: 1.0/3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low Input Current ORDERING INFORMATION KK74LVU04N Plastic KK74LVU04D SOIC TA = -40 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Input A L H PIN 14 =VCC PIN 7 = GND Output Y H L 1 KK74LVU04 MAXIMUM RATINGS* Symbol VCC IIK * IO * ICC IGND PD Tstg TL * 1 2 Parameter DC supply voltage (Referenced to GND) DC input diode current DC output diode current DC output source or sink current -bus driver outputs DC VCC current for types with - bus driver outputs DC GND current for types with - bus driver outputs Power dissipation per package, plastic DIP+ SOIC package+ Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) Value -0.5 / +7.0 20 50 25 50 50 750 500 -65 / +150 260 Unit V mA mA mA mA mA mW C C IOK * 3 Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 70 to 125C SOIC Package: : - 8 mW/C from 70 to 125C *1: VI < -0.5V or VI > VCC+0.5V *2: Vo < -0.5V or Vo > VCC+0.5V *3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time 1.0 VVCC <2.0 V 2.0 VVCC <2.7 V 2.7 VVCC <3.6 V 3.6 VVCC 5.5 V Min 1.0 0 -40 0 0 0 0 Max 5.5 VCC +125 500 200 100 50 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LVU04 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol VIH Parameter High-Level Input Voltage Test Conditions VCC, V 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 VI = VIH or VIL I0=-100 A 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 Guaranteed Limit 25C min max 1.0 1.6 2.4 2.4 2.4 3.6 4.4 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 0.2 0.4 0.5 0.5 0.5 0.9 1.1 -40C / 85C min max 1.0 1.6 2.4 2.4 2.4 3.6 4.4 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.40 0.2 0.4 0.5 0.5 0.5 0.9 1.1 -40C / 125C min max 1.0 1.6 2.4 2.4 2.4 3.6 4.4 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 0.2 0.4 0.5 0.5 0.5 0.9 1.1 Unit V VIL Low -Level Input Voltage V VOH High-Level Output Voltage V VI = VIH or VIL I0=-6.0 mA VI = VIH or VIL I0=-12 mA VOL Low-Level Output Voltage VI = VIH or VIL I0=100 A 4.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 3.70 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 3.60 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.40 3.50 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.50 V VI = VIH or VIL I0=6.0 mA VI = VIH or VIL I0=12 mA IIL Low-Level Input Leakage Current VI=0 V 4.5 - 0.40 - 0.55 - 0.65 5.5 - -0.1 - -1.0 - -1.0 A 3 KK74LVU04 DC ELECTRICAL CHARACTERISTICS (continuation) Symbol IIH Parameter High-Level Input Leakage Current Quiescent Supply Current (per Package) Additional Quiescent Supply Current on input Test Conditions VI= V VCC, V 5.5 Guaranteed Limit 25C min max 0.1 -40C / 85C min max 1.0 -40C / 125C min max 1.0 Unit ICC VI=0 or V IO = 0 A VI = V 0.6V 5.5 - 4.0 - 20 - 40 A ICC1 2.7 3.6 - 0.2 0.2 - 0.5 0.5 - - 0.85 0.85 mA AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH =tHL = 2.5 ns, RL=1 k) Guaranteed Limit Symbol Parameter Test Conditions VI=0 V or V1 tLH = tHL =2.5 ns L = 50 pF RL = 1 k VCC V min tPHL (tPLH) Propagation Delay, Input A to Output Y (Figure 1 ) 1.2 2.0 2.7 3.0 4.5 max 70 22 16 13 11 min max 80 26 19 15 13 25C -40C / 85C -40C / 125C min max 100 31 23 18 16 Unit ns CI CPD Input Capacitance 5.5 - 7.0 - - - - pF pF Power Dissipation Capacitance (Per Inverter) =25, VI=0V or VCC 36 Used to determine the no-load dynamic power consumption: PD = CPDVCC2fI+ (CLVCC2fo), fI - input frequency, fo - output frequency (MHz) (CLVCC2fo) - sum of the outputs 4 KK74LVU04 tHL 0.9 VX 0.1 0.9 VX tLH V1 0.1 Input tPHL tPLH GND VOH Output Y VX=0.5 VCC VY VY VOL Figure 1. Switching Waveforms VCC VI PULSE GENERATOR DEVICE UNDER TEST VO Termination resistance RT - should be equal to ZOUT of pulse generators RT CL RL Figure 2. Test circuit 5 KK74LVU04 N SUFFIX PLASTIC DIP (MS - 001AA) A 14 8 B 1 7 Dimension, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 10 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLANE G H H J M J K L M N NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 012AB) Dimension, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLANE H J F M J K M P R 8 0.25 0.25 6.2 0.5 NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. 6 |
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